There is an increasing demand for semiconductor memory devices that can offer fast random access and realize large storage capacity and high degree of integration. A representative example of such a semiconductor memory devices is a flash memory commonly used in devices such as portable electronic appliances. Moreover, semiconductor memory devices in which a nonvolatile material is substituted for a capacitor of a dynamic random access memory (DRAM) have been increasingly produced.
Examples of the semiconductor memory devices in which the nonvolatile material is substituted for the capacitor of the DRAM include a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase change memory device using chalcogenide alloys and the like. Particularly, a resistance variable memory device, such as the phase change memory device, has a relatively simple manufacturing process and can realize a memory of a large amount of capacity at a low cost.
FIG. 1 is a view illustrating a memory cell of a typical resistance variable memory device, in accordance with the prior art. Referring to FIG. 1, a memory cell 10 of a resistance variable memory device includes a variable resistor C and an access transistor M.
The variable resistor C is connected to a bit line BL. The access transistor M is connected between the variable resistor C and a ground. A word line WL is connected to a gate of the access transistor M. When a predetermined voltage is applied to the word line WL, the access transistor M turns on. When the access transistor M turns on, a current Ic is supplied to the variable resistor C through the bit line BL.
The variable resistor C includes a phase change material (not shown). The phase change material has two stabilized states, that is, a crystal state and an amorphous state according to a temperature. The phase change material is changed into the crystal state or the amorphous state according to the current Ic supplied through the bit line BL. A phase change memory device programs data using such properties of the phase change material.
FIG. 2 is a graph illustrating characteristics of a phase change material, in accordance with the prior art. Referring to FIG. 2, reference numeral 1 represents a condition for allowing a phase change material GST to become an amorphous state, and reference numeral 2 represents a condition for a crystal state.
When the phase change material GST is heated at a temperature above a melting temperature Tm for a first duration T1 by supplying a current thereto and is quickly quenched, the phase change material GST changes to the amorphous state. The amorphous state is generally called a reset state and stores data “1”. On the other hand, when the phase change material GST is heated at temperature between the melting temperature Tm and a crystallization temperature Tc for a period of time between the first duration T1 and a second duration T2 and is slowly quenched, the phase change material GST changes to the crystal state. The crystal state is generally called a set state and stores data “0”. A resistance value of the memory cell is changed according to an amorphous volume of the phase change material GST. The resistance value of the memory cell is the highest in the amorphous state and the lowest in the crystal state.
In recent years, a technology for storing two or more bit data in one memory cell has been developed. This memory cell is called a multi level cell (MLC) and has multi states according to the distribution of resistance. In a resistance variable memory device, the MLC further includes intermediate states between the reset state and the set state. A programming method of a resistance variable memory device having the MLC is disclosed in U.S. Pat. No. 6,625,054 (hereinafter, referred to as '054 patent).
FIGS. 3A-3D are graphs illustrating a programming method of a resistance variable memory device having a typical MLC, where each of FIGS. 3A-3D represents a different set of programming signals, in accordance with the prior art. The programming method as illustrated in FIGS. 3A-3D is disclosed in the '054 patent. Referring to FIGS. 3A-3D, different times T0-T11 are denoted on the TIME axis and currents I0 (min), I1 (max in FIGS. 3A,B,D) and I2 (max in FIG. 3C) are denoted on the CURRENT axis. The memory cell represented in each figure has four states according to a falling time of a program pulse. In case where the memory cell is in a reset state is called a state “11”, and in case where the memory cell is in a set state is called a state “00”. The memory cell further has a state “10” and a state “01” according to an amorphous volume of a phase change material.
According to the '054 patent, a phase change memory device programs two bits in one memory cell by controlling a falling time of a current pulse supplied into the memory cell. The '054 patent uses a characteristic that the amorphous volume of the phase change material decreases as the falling time of the current pulse increases.
There should be no difference between a resistance value at several nanoseconds after programming and a resistance value at several or several tens of days after programming so that the typical resistance variable memory device, such as the '054 patent, performs a normal MLC operation. However, the resistance value of the resistance variable memory device is changed according to a lapse of time due to the property of the phase change material (GST). This phenomenon is called resistance drift, which can negatively affect the reliability of the device. It would be advantageous to devise a resistance variable memory device that minimizes or substantially eliminates resistance drift.